The present invention relates to a semiconductor memory device having a memory cell array block selection function and more particularly to a device for selecting memory cell array blocks with low power consumptions.
Dynamic RAM (DRAM) can be widely divided into a memory cell array portion and a peripheral circuit portion. In such a DRAM, the power consumption ratio of the memory cell array portion to the peripheral circuit portion is normally 100 to 30. The power consumed in the memory cell array is generally caused by a write operation of writing data into a memory cell, which has been read out from a different memory cell and is determined by the refresh cycles and the number of divided memory cell array blocks. When the power is consumed abruptly, the power noises may be generated. Therefore, it is very important to reduce the power consumption in a semiconductor memory device with high speed and high density.
Referring to FIG. 1A, the configuration of a known semiconductor memory chip with a block selection function is shown, wherein four main blocks ULA, URA, LLA, LRA are respectively divided into thirty-two subblocks. As shown in FIG. 1A, the conventional semiconductor memory device drives only a specific number of subblocks within each main block to distribute the entire power consumptions. For example, the subblocks SB1 and SB17 are selected in the upper left block ULA; the subblocks SB33 and SB 49 in the upper right block URA; the subblocks SB65 and SB77 in the lower left block LLA; and the subblocks SB96 and SB112 in the lower right block LRA.
Conventional semiconductor memory devices employing the partial activation technique as shown in FIG. 1A are disclosed in U.S Pat. Nos. 4,528,646 and 4,569,036. Referring to FIG. 1B, another conventional semiconductor memory device disclosed in U.S. Pat. No. 4,528,646 is shown. It is well shown in the drawing that the device is partially activated by first through fourth selection circuits which are controlled by a selection control signal. The first selection circuit controls selectively the left or right bit line precharge circuit to activate a bit line pair corresponding to a selected subblock of the left or right memory cell array. The second selection circuit activates a sense amplifier corresponding to a memory cell of the selected subblock. The third selection circuit activates a data bus line corresponding to the selected subblock, and the fourth selection circuit activates an input/output precharge circuit corresponding to the selected subblock. Namely, by driving the bit line precharge circuit, the sense amplifier, the data bus line, and the input/output precharge circuit which correspond to the subblocks SB1, SB17, SB33, SB49, SB65, SB77, SB96 and SB112, the memory cell array (which correspond to the subblocks of the respect main blocks of FIG. 1) is partially activated.
Referring now to FIG. 1C, a conventional semiconductor memory device disclosed in U.S. Pat. No. 4,569,036 is shown. The device is a little different from the device shown in FIG. 1B, but a signal RSBS (randomly selected bit signal) generated from a row address buffer is applied to a driver circuit and sense amplifiers corresponding to the respective memory cell array are controlled by the driver circuit. It is noted that the device of FIG. 1C also has a partial activation function similarly to the device of FIG. 1A.
The memory device having the partial activation function has an advantage of reducing the noises by distributing the total power consumption of the memory cell array. However, in recent a dual pad and a double metal line are used for the power supply voltage terminal Vcc and/or the ground voltage terminal Vss because of the high density of the memory device, so that the noises are not considerably reduced in comparison with the device in which the power consumptions of the subblocks are not distributed. Instead, because in the case where the subblocks are evenly distributed the peripheral circuit for controlling the subblocks are additionally required, the entire peripheral circuits must be enabled even if only some of the subblocks in each main block are activated as shown in FIG. 1. This will increase not only the power consumption but also the peak current of the peripheral circuits. Such undesirable effect gets worse as the chip size increases, because the load of the wires of a control circuit for driving the subblocks is usually influenced by the capacitance formed between the metal and the substrate. Namely, as the chip size of the memory device increases, the transmission distance of the signals of the control circuit becomes longer and the areas of the metal and the substrate also increase. The foregoing relation can be understood from an equation of C=A/d, where A is the area of the metal and the substrate, and d is the space between the wires. Further, it can be appreciated from the related equations of i=C(dv/dt) and p=iv that the power consumption increases.